Add_rca_4

程式碼
module test_Add_rca_4();
reg [3:0] a,b;
reg c_in;
wire [3:0] sum;
wire c_out;
initial
begin
$display($time,,"c_out=%b c_in4=%b c_in3=%b c_in2=%b c_in=%b,sum[0]=%b",
c_out,M1.c_in4,M1.c_in3,M1.c_in2,c_in,sum[0])
end
initial
begin
a=0;
b=0;
c_in=0;
#500 $finish;
end
always
#20 a=~a;
always
#30 b=~b;
always
#40 c_in=~c_in;
initial
begin
end
Add_rca_4 M1 (sum,c_out,a,b,c_in);
endmodule
module Add_rca_4 (sum,c_out,a,b,c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire c_out,c_in4,c_in3,c_in2;
Add_full G1 (sum[0],c_in2,a[0],b[0],c_in);
Add_full G2 (sum[1],c_in3,a[1],b[1],c_in2);
Add_full G3 (sum[2],c_in4,a[2],b[2],c_in3);
Add_full G4 (sum[3],c_out,a[3],b[3],c_in4);
endmodule
module Add_full (sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;
Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
module Add_half (sum,c_out,a,b);
input a,b;
output c_out,sum;
assign {c_out,sum}=a+b;
endmodule
===================================================================
這次的程式很困難,大概做完了
訊號不知道有沒有給錯

P.84

程式碼
module top;
reg A,B;
wire y_out;
connet_1 m1(y_out,A,B);
initial
begin
A=0;
B=0;
#2000 $finish;
end
always
#50 A=~A;
always
#25 B=~B;
endmodule

module connet_1(y_out,A,B);
input A,B;
output y_out;
wire y1;
not (y1,A);
nand (y_out,y1,B);
endmodule

P.75 Nand_Latch

程式碼
module test_nand_latch_1;
reg preset,clear;
wire q,qbar;
nand_latch_1 m1(q,qbar,preset,clear);
initial
begin
$monitor($time,"preset=%b clear=%b q=%b qbar=%b",preset,clear,q,qbar);
end
initial
begin
#10 preset =0;clear=1;
#10 preset =1;
#10 clear =0;
#10 clear =1;
#10 preset =0;
$stop;
end
initial
#2000 $finish;
endmodule

module nand_latch_1(q,qbar,preset,clear);
input preset,clear;
output q,qbar;
nand G1(q,preset,qbar);
nand G2(qbar,clear,q);
endmodule

===================================================================
這次的程式碼課本有很多錯誤
修改了很多錯誤才成功

P.68 Inertial Delay AND Event DE-SCHEDULING

程式碼
module top;
reg x_in1,x_in2,y;
wire y_out;
AOI_2_unit m1(x_in1,x_in2,y_out);
initial
begin
x_in1=0;
x_in2=0;
y=0;
#2000 $finish;
end
always
#50 x_in1=~x_in1;
always
#50 x_in2=~x_in2;
always
#50 y=~y;
endmodule

module AOI_2_unit(x_in1,x_in2,y_out);
input x_in1,x_in2;
output y_out;
wire y1;
and #3 (y1,x_in1,x_in2);
nor #2 (y_out,y1);
endmodule
===================================================================
這次的程式讓我了解Delay是如何運作

比較器

程式碼
module top;
reg A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_str m1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
initial
begin
A0=0;
A1=0;
B0=0;
B1=0;
#2000 $finish;
end
always
#10 A0=~A0;
always
#20 A1=~A1;
always
#30 B0=~B1;
always
#40 B1=~B1;
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_lt_B,w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule
===================================================================
今天練習了比較器
對verilog也越來越熟悉了

Flip_flop

module top;
reg data_in,clk,set,rst;
wire q;
Flip_flop m1(q,data_in,clk,set,rst);
initial
begin
data_in=0;
clk=0;
set=1;
rst=0;
#500 $finish;
end
always
#50 data_in=~data_in;
always
#20 clk=~clk;
always
#30 set=~set;
always
#40 rst=~rst;
endmodule
module Flip_flop(q,data_in,clk,set,rst);
input data_in,clk,set,rst;
output q;
reg q;
always @ (posedge clk)
begin
if (rst==0)q=0;
else
if (set==0)q=1;
else
q=data_in;
end
endmodule

and_4rtl

程式碼
module top;
reg x_in1,x_in2,x_in3,x_in4;
wire y_out;
and4_rtl m1(y,x_in1,x_in2,x_in3,x_in4);
initial
begin
x_in1=0;
x_in2=0;
x_in3=0;
x_in4=0;
#1000 $finish;
end
always
#4 x_in1=~x_in1;
always
#8 x_in2=~x_in2;
always
#16 x_in3=~x_in3;
always
#32 x_in4=~x_in4;
endmodule
module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out= x_in1 & x_in2 & x_in3 & x_in4;
endmodule

NAND delay

程式碼
module top;
reg A1,B1;
wire o;
nanf201 G1(o,A1,B1);
initial
begin
A1=0;
B1=0;
#500 $finish;
end
always
#50 A1=~A1;
always
#30 B1=~B1;
endmodule
module nanf201(o,A1,B1);
input A1,B1;
output o;
nand(o,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.5:7.34;
(A1=>o)=(Tpd_0_1,Tpd_1_0);
(B1=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
===================================================================
這次實作讓我暸解訊號的delay如何運作

Add_Full

程式碼
module top;

reg a,b,c_in;

wire sum,c_out,w1,w2,w3;

Add_half M1(w1,w2,a,b);

Add_half M2(sum,w3,w1,c_in);

or(c_out,w2,w3);

initial

begin

a=0;

b=0;

c_in=0;

#2000 $finish;

end

always

#200 c_in=~c_in;

always

#50 a=~a;

always

#100 b=~b;

endmodul

emodule Add_half(sum,c_out,a,b);

input a,b;

output sum,c_out;

xor (sum,a,b);

nand (c_out_bar,a,b);

not (c_out,c_out_bar);

endmodule
===================================================================

經過多次歷練

現在對程式也有一定了解
寫程式的速度也越來越快
這次的全加器在不了解的地方

也很快就解決了

這次用2個半加器合成一個全加器

滿有意思的