比較器

程式碼
module top;
reg A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_str m1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
initial
begin
A0=0;
A1=0;
B0=0;
B1=0;
#2000 $finish;
end
always
#10 A0=~A0;
always
#20 A1=~A1;
always
#30 B0=~B1;
always
#40 B1=~B1;
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_lt_B,w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule
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今天練習了比較器
對verilog也越來越熟悉了