Add_rca_4

程式碼
module test_Add_rca_4();
reg [3:0] a,b;
reg c_in;
wire [3:0] sum;
wire c_out;
initial
begin
$display($time,,"c_out=%b c_in4=%b c_in3=%b c_in2=%b c_in=%b,sum[0]=%b",
c_out,M1.c_in4,M1.c_in3,M1.c_in2,c_in,sum[0])
end
initial
begin
a=0;
b=0;
c_in=0;
#500 $finish;
end
always
#20 a=~a;
always
#30 b=~b;
always
#40 c_in=~c_in;
initial
begin
end
Add_rca_4 M1 (sum,c_out,a,b,c_in);
endmodule
module Add_rca_4 (sum,c_out,a,b,c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire c_out,c_in4,c_in3,c_in2;
Add_full G1 (sum[0],c_in2,a[0],b[0],c_in);
Add_full G2 (sum[1],c_in3,a[1],b[1],c_in2);
Add_full G3 (sum[2],c_in4,a[2],b[2],c_in3);
Add_full G4 (sum[3],c_out,a[3],b[3],c_in4);
endmodule
module Add_full (sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;
Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
module Add_half (sum,c_out,a,b);
input a,b;
output c_out,sum;
assign {c_out,sum}=a+b;
endmodule
===================================================================
這次的程式很困難,大概做完了
訊號不知道有沒有給錯