and_4rtl

程式碼
module top;
reg x_in1,x_in2,x_in3,x_in4;
wire y_out;
and4_rtl m1(y,x_in1,x_in2,x_in3,x_in4);
initial
begin
x_in1=0;
x_in2=0;
x_in3=0;
x_in4=0;
#1000 $finish;
end
always
#4 x_in1=~x_in1;
always
#8 x_in2=~x_in2;
always
#16 x_in3=~x_in3;
always
#32 x_in4=~x_in4;
endmodule
module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out= x_in1 & x_in2 & x_in3 & x_in4;
endmodule