Flip_flop

module top;
reg data_in,clk,set,rst;
wire q;
Flip_flop m1(q,data_in,clk,set,rst);
initial
begin
data_in=0;
clk=0;
set=1;
rst=0;
#500 $finish;
end
always
#50 data_in=~data_in;
always
#20 clk=~clk;
always
#30 set=~set;
always
#40 rst=~rst;
endmodule
module Flip_flop(q,data_in,clk,set,rst);
input data_in,clk,set,rst;
output q;
reg q;
always @ (posedge clk)
begin
if (rst==0)q=0;
else
if (set==0)q=1;
else
q=data_in;
end
endmodule