P.84

程式碼
module top;
reg A,B;
wire y_out;
connet_1 m1(y_out,A,B);
initial
begin
A=0;
B=0;
#2000 $finish;
end
always
#50 A=~A;
always
#25 B=~B;
endmodule

module connet_1(y_out,A,B);
input A,B;
output y_out;
wire y1;
not (y1,A);
nand (y_out,y1,B);
endmodule

P.75 Nand_Latch

程式碼
module test_nand_latch_1;
reg preset,clear;
wire q,qbar;
nand_latch_1 m1(q,qbar,preset,clear);
initial
begin
$monitor($time,"preset=%b clear=%b q=%b qbar=%b",preset,clear,q,qbar);
end
initial
begin
#10 preset =0;clear=1;
#10 preset =1;
#10 clear =0;
#10 clear =1;
#10 preset =0;
$stop;
end
initial
#2000 $finish;
endmodule

module nand_latch_1(q,qbar,preset,clear);
input preset,clear;
output q,qbar;
nand G1(q,preset,qbar);
nand G2(qbar,clear,q);
endmodule

===================================================================
這次的程式碼課本有很多錯誤
修改了很多錯誤才成功

P.68 Inertial Delay AND Event DE-SCHEDULING

程式碼
module top;
reg x_in1,x_in2,y;
wire y_out;
AOI_2_unit m1(x_in1,x_in2,y_out);
initial
begin
x_in1=0;
x_in2=0;
y=0;
#2000 $finish;
end
always
#50 x_in1=~x_in1;
always
#50 x_in2=~x_in2;
always
#50 y=~y;
endmodule

module AOI_2_unit(x_in1,x_in2,y_out);
input x_in1,x_in2;
output y_out;
wire y1;
and #3 (y1,x_in1,x_in2);
nor #2 (y_out,y1);
endmodule
===================================================================
這次的程式讓我了解Delay是如何運作

比較器

程式碼
module top;
reg A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
compare_2_str m1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
initial
begin
A0=0;
A1=0;
B0=0;
B1=0;
#2000 $finish;
end
always
#10 A0=~A0;
always
#20 A1=~A1;
always
#30 B0=~B1;
always
#40 B1=~B1;
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_lt_B,w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule
===================================================================
今天練習了比較器
對verilog也越來越熟悉了

Flip_flop

module top;
reg data_in,clk,set,rst;
wire q;
Flip_flop m1(q,data_in,clk,set,rst);
initial
begin
data_in=0;
clk=0;
set=1;
rst=0;
#500 $finish;
end
always
#50 data_in=~data_in;
always
#20 clk=~clk;
always
#30 set=~set;
always
#40 rst=~rst;
endmodule
module Flip_flop(q,data_in,clk,set,rst);
input data_in,clk,set,rst;
output q;
reg q;
always @ (posedge clk)
begin
if (rst==0)q=0;
else
if (set==0)q=1;
else
q=data_in;
end
endmodule

and_4rtl

程式碼
module top;
reg x_in1,x_in2,x_in3,x_in4;
wire y_out;
and4_rtl m1(y,x_in1,x_in2,x_in3,x_in4);
initial
begin
x_in1=0;
x_in2=0;
x_in3=0;
x_in4=0;
#1000 $finish;
end
always
#4 x_in1=~x_in1;
always
#8 x_in2=~x_in2;
always
#16 x_in3=~x_in3;
always
#32 x_in4=~x_in4;
endmodule
module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out= x_in1 & x_in2 & x_in3 & x_in4;
endmodule