Flip_flop

程式碼
module top;
reg data_in,clk;
wire q;
Flip_flop m1(q,data_in,clk,rst);
initial
begin
data_in=0;
clk=0;
#2000 $finish;
end
always
#100 data_in=~data_in;
always
#30 clk=~clk;
endmodule
module Flip_flop (q,data_in,clk,rst);
input data_in,clk,rst;
output q;
reg q;
always @(posedge clk)
begin
if(rst==1) q=0;
else q=data_in;
end
endmodule
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這次上課學會了如何判斷波形是否正確